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ADV7403
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
P32
1
75
AIN12
P31
INT
CS/HS
DGND
DVDDIO
P15
P14
P13
P12
DGND
DVDD
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P11
P10
P9
P8
P27
P7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN 1
ADV7403
LQFP
TOP VIEW
(Not to Scale)
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AIN5
AIN11
AIN4
AIN10
TEST0
CAPC2
CAPC1
BIAS
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
TEST1
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
SOG
FB
Figure 7. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 2, 83, 84, 87, 88,
Mnemonic
P31 to P40
Type 1
I
Description
Video Pixel Input Port.
95 to 97, 100
3
4
INT
CS/HS
O
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin triggers. The set of events that triggers an interrupt is under user control.
Digital Composite Synchronization Signal (CS). The CS pin can be selected while in CP
mode.
Horizontal Synchronization Output Signal (HS). The HS pin can be selected while in
SDP or CP modes.
5, 11, 17, 40, 89
6, 18
7 to 10, 22, 23,
25 to 28, 41, 42,
DGND
DVDDIO
P2 to P9, P12 to P19
G
P
O
Digital Ground.
Digital Input/Output Supply Voltage (3.3 V).
Video Pixel Output Port.
91 to 94
12, 39, 90
13, 14, 20, 21, 24,
29 to 34, 43 to 45
DVDD
P0 to P1, P10 to P11,
P20 to P29
P
I/O
Digital Core Supply Voltage (1.8 V).
Video Pixel Input/Output Port.
Rev. B | Page 10 of 20
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